1. Field of the Invention
The present invention relates to a memory drive system of a d.c. (direct current) type of plasma display panel (DC-PDP).
2. Description of the Background Art
Hitherto, as the state of the field, there is published a document: Hiroshi Murakami, et al., "Study on a Color Graphic Gas-Discharge Pulse Memory Panel", Transactions of The Institute of Electronics, Information and Communication Engineers of Japan, C-II, Vol. J73-C-II, No. 11, pp. 794-802 (November 1990).
FIG. 2 is a perspective illustration of a conventional DC-PDP shown in the above-referenced document. In the figure, the DC-PDP is arranged between a rear plate 1 and a front plate 2. On the rear plate 1, there are formed a plurality of cathodes 3.sub.1 -3.sub.I (I is a positive integer) which are arranged substantially in parallel with one another. Each of the cathodes 3.sub.1 -3.sub.I is a linear electrode. On the front plate 2, there are formed a plurality of anodes 4.sub.1 -4.sub.J (J is also a positive integer) which are arranged substantially in parallel with one another. Each of the anodes 4.sub.1 -4.sub.J is a linear electrode. The cathodes 3.sub.1 -3.sub.I and the anodes 4.sub.1 -4.sub.J are located over and adjacent each other in an intersecting relation. A barrier 5 is interposed between the rear plate 1 and the front plate 2 to provide a certain interval therebetween. A mixed gas of, for example, helium (He) and xenon (Xe), as the discharge gas, is enclosed between the rear plate 1 and the front plate 2.
There are provided discharge cells 6 at the cross points of the cathodes 3.sub.1 -3.sub.I and the anodes 4.sub.1 -4.sub.J. That is, a plurality of discharge cells 6 is arranged as a matrix. A phosphor 7 is disposed for each discharge cell 6 in each of the areas in which the front plate 2 is adjacent to the respective anodes 4.sub.1 -4.sub.J. The respective discharge cells 6 are partitioned by the barrier 5. In the barrier 5 partitioning the adjacent discharge cells 6, there are formed cutting sections in a direction, to which each of the linear anodes extends, to provide priming slits 8 each serving as a space for coupling the adjacent discharge cells 6 to one another.
FIG. 3 is a time chart showing drive waveforms for the DC-PDP shown in FIG. 2. The reference letter A.sub.j (1.ltoreq.j.ltoreq.J) shown in FIG. 3 denotes voltage waveforms to be applied to the anode 4.sub.j ; and K.sub.i (1.ltoreq.i.ltoreq.I) and K.sub.i+1 denote voltage waveforms to be applied to the cathodes 3.sub.i and 3.sub.i+1, respectively. Always applied to the anode 4.sub.j are a bias voltage V.sub.A (e.g. 60 volts (V)) and a voltage V.sub.SP (e.g. 135 V) of a sustain pulse (SP) train of a period T. Similarly, the bias voltage V.sub.A and the voltage V.sub.SP of the sustain pulse (SP) train are applied to other anodes 4.sub.1 to 4.sub.j-1 and 4.sub.j+1 to 4.sub.J. On the other hand, an auxiliary pulse AK of a peak voltage V.sub.AK (e.g. -230 V) is applied to the cathode 3.sub.i.
When a potential between the anode 4.sub.j and the cathode 3.sub.i becomes 290 V of the discharge voltage by application of the auxiliary pulse AK to the cathode 3.sub.i, a short period of priming discharge occurs forcibly, first, in a line of discharge cells 6. Subsequently, the sequential application of the auxiliary pulse AK to the adjacent cathodes 3.sub.i+1, 3.sub.i+2, . . . causes the priming discharge to sequentially shift. At that time, the charged particles diffuse through the priming slit 8 to the adjacent discharge cell 6. This brings about such a condition that the discharge additionally is easy to take place in the adjacent discharge cell 6. Thus, a stable shift of the priming discharge can be realized. After application of the auxiliary pulse AK to the cathodes, the potential of the cathode 3.sub.i is set up to 0 V so as to prevent the discharge. In this manner, the charged particles within the discharge cell are reduced with the passage of time.
After an erasing condition is maintained during a period of time T.sub.0, an anode write pulse WA is applied to the anode 4.sub.j, and simultaneously, a cathode write pulse WK is applied to the cathode 3.sub.i. A voltage V.sub.WA of the anode write pulse WA is, for example, 110 V, and a voltage V.sub.WK of the cathode write pulse WK is, for example, -230 V. The discharge cell 6, to which both the anode write pulse WA and the cathode write pulse WK are applied, form a write discharge. This write discharge is formed promptly, since the charged particles created in the priming discharge before time T.sub.0 remain in the discharge cell 6. When the write discharge is terminated, a voltage V.sub.M (e.g. -80 V) is applied to the cathode 3.sub.i.
While the charged particles created in the write discharge are gradually decreased with the passage of time, a lot of charged particles still remain in the discharge cell 6 immediately after the write discharge. It is thus possible to form a discharge even with a voltage lower than a write discharge voltage. Specifically, after the write discharge, a discharge is formed even with a sustained discharge voltage (V.sub.SP -V.sub.M =215 V) lower than the write discharge voltage (V.sub.WA -V.sub.WK =340 V), so that a sustain discharge is continued on a pulse basis by the sustain pulses SP of the anode 4.sub.j and the voltage V.sub.M of the cathode 3.sub.i.
When the sustain discharge is stopped, the voltage of the cathode 3.sub.i is forcibly set up to 0 V. On the other hand, in the discharge cell 6 to which no write pulse is applied, the charged particles almost disappear. Thus, the pulse discharge is not formed with a voltage lower than the write discharge voltage.
Control is provided such that a priming discharge period .tau..sub.T, a writing discharge period .tau..sub.W, .tau..sub.K, and a period .tau..sub.SP of the sustain pulse SP do not overlap each other.
However, the conventional memory drive scheme of a DC-PDP involves the following drawbacks. According to the conventional memory drive scheme of a DC-PDP, even if voltage waveforms are applied to the respective cathodes 3.sub.1+1, 3.sub.i+1, . . . on a pulse shift basis, there is a need to adopt a time division on a period T of time in order to provide such a control that timings of the priming discharge, the writing discharge and the the sustain discharge do not overlap each other. This involves a limit in reducing an access time for a line. Thus, it will be difficult to provide a display of a sufficient gray level. Further, according to the conventional memory drive scheme of a DC-PDP, levels of a signal to be applied to the anode 4.sub.j take three values of a voltage V.sub.A, a voltage V.sub.WA and a voltage V.sub.SP, and levels of a signal to be applied to the cathode 3.sub.i also take three values of 0 V, a voltage V.sub.M and voltages V.sub.AK, V.sub.WK. Those voltages are selectively used on a changeover basis. This causes drive circuits for driving the cathodes 3.sub.1 -3.sub.I and anodes 4.sub.1 -4.sub.J to be complicated and obliged to be expensive. For example, in order to drive the respective cathodes 3.sub.1 -3.sub.I and the respective anodes 4.sub.1 -4.sub.J with three values, there are needed three transistors each having a high withstand voltage for each of the cathodes 3.sub.1 -3.sub.I and the anodes 4.sub.1 -4.sub.J. This causes the drive circuits to be expensive.